1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and in particular to a charge coupled device (CCD) and a fabrication method thereof which are capable of preventing a charge-up phenomenon which occurs during a plasma process.
2. Description of the Background Art
In order to increase the intensity of a semiconductor device, it is necessary to reduce a design rule. Namely, a fabrication process margin should be reduced. In order to satisfy a reduced design rule, a pattern should be accurately formed when fabricating a semiconductor device. The etching process which uses a plasma such as a reactive ion etching (RIE), etc. has been widely used for implementing the above-described accurate pattern formation. However, the etching process which uses a plasma is capable of accurately forming a pattern. However, this process has a disadvantage in that it affects a semiconductor device. Namely, since a wafer is exposed to a non-uniform plasma environment, it is impossible to obtain a uniform characteristic of a semiconductor device. In addition, the devices are applied with an electrical stress due to a charge-up which occurs on the upper surface of the wafer for thereby decreasing the operational performance of the semiconductor device.
The structure of a known semiconductor device and a fabrication method thereof will now be explained with reference to the accompanying drawings and the problems that an electric charge which is induced by an etching affects the semiconductor device will be explained.
FIG. 1 is a plan view illustrating the known semiconductor device.
A center portion 2 and a peripheral portion 3 of a semiconductor device are formed on a semiconductor substrate 1. The center portion 2 of the semiconductor device is formed of a photo metallic layer formed of a photo diode 21 which is a passing-through portion which passes through light and a blocking portion 22 which does not pass through light. In addition, a pad 31 is formed on the peripheral portion 3 of the semiconductor device for electrically connecting an external circuit and the semiconductor device.
FIG. 2 is a cross-sectional view taken along the line II--II' of FIG. 1 and illustrating a peripheral portion of a known semiconductor device.
A p-well 11 (hereinafter called Electrostatic Discharge (ESD) p-well 11) is formed in the semiconductor substrate 1 for implementing an electrostatic discharge, and a device isolation region "a" is formed on both marginal portions of the ESD-well 11. N-type diffusion layers 12 and 13 and a p-type diffusion layer 14 are formed in the ESD p-well 11. A first insulation layer 15 is formed on the upper surface of the semiconductor substrate 1. The first insulation layer 15 is formed in a double layer structure of an HLD layer 15a and a BPSG layer 15b. Contact holes 12a and 13aare formed on the n-type diffusion layers 12 and 13, and a contact hole 14a is formed on the p-type diffusion layer 14. Metallic wiring portions 12b, 13b and 14b are formed in the contact holes 12a, 13a and 14a and on the upper surface of the insulation layer, respectively. A second insulation layer 16 is formed on the upper surfaces of the metallic wiring portions 12b, 13b and 14b and the upper surface of the first insulation layer 15. The second insulation layer 16 is formed of a P--SiO film.
A P--SiN film is formed on the upper surface of the second insulation layer 16 as a protection layer 17 for protecting the semiconductor device. A planarizing layer 18 is formed on the upper surface of the protection layer 17 for planarizing the semiconductor device. A pad hole 19 is formed on the metallic wiring portion 12bfor forming the pad 31, and a metallic layer is deposited in the pad hole 19 for thereby forming a pad 31.
The fabrication method of a semiconductor device will now be explained.
First, a p-type dopant ion is implanted into the n-type semiconductor substrate 1 for forming an ESD p-well 11. A device isolation region "a" is formed on the upper surface of the semiconductor substrate 1 and at both sides of the p-well 2 using a LOCOS process. Next, n-type diffusion layers 12 and 13 are formed in the p-well 2 and then a p-type diffusion layer 14 is formed. Thereafter, a HLD 15a and BPSG 15b are sequentially formed for forming the first insulation film 15. Contact holes 12a, 13a and 14a are formed to expose the upper surfaces of the n-type diffusion layers 12 and 13 and the p-type diffusion layer 14 by etching the first insulation film 15.
When forming the contact holes 12a, 13aand 14a, the etching operation is performed using a plasma. A metallic layer is coated in the interior of the contact holes 12a, 13a and 14a and on the upper surface of the second insulation film 15b for forming a connection wiring portion between the devices and then are patterned for thereby forming metallic wiring portions 12b, 13b and 14b. When patterning the metallic layer for forming the metallic wiring portions 12b, 13b and 14b, the etching operation is performed using a plasma. Thereafter, the second insulation film 16 is formed on the upper surfaces of the first insulation film 15 and the metallic wiring portions 12b, 13b and 14b. A blocking layer, namely, a photo metallic layer (not shown) is formed on the upper surface of the second insulation film 16 for blocking light. At this time, the second insulation film 16 is a P--SiO film, and the photo metallic layer (not shown) is a metallic film such as a tungsten (W), TiW, TiN, Al, MoSix, etc. The photo metallic layer (not shown) formed on the passing through portion 21 and the peripheral portion 3 of the semiconductor substrate are etched and removed using a plasma. Namely, the photo metallic layer is formed only on the upper surface of the center portion 2 of the semiconductor device except the photo diode 21. The CCD is a device for converting light into an electrical signal. Since the CCD receives light through the photo diode, the region except the region of the photo diode should be blocked from light. However, since the peripheral portion 3 of the semiconductor device does not need to block light, the photo metallic layer formed on the upper surface of the peripheral portion 3 is generally etched and removed. The P-SiN layer is formed as the protection film 17 for protecting the semiconductor device, and the pad hole 19 is formed on the upper surface of the metallic wiring portion 12b connected with the n-type diffusion layer 12 for forming the pad connecting the device formed on the semiconductor substrate 1, namely, the n-type diffusion layer 12 and the external circuit. Thereafter, the planarizing layer 18 is formed in the pad hole 19 and on the upper surface of the protection layer 17 for forming a u-lens (not shown) of the photo diode 21. Thereafter, the planarizing layer 18 is etched so that the upper surface of the metallic wiring portion 12b is exposed, and then the pad hole 19 is formed, and the metallic layer is deposited in the pad hole 19 for thereby forming a pad 31.
The etching process is repeatedly performed using a plasma, and negative electric charges are charged up on the upper surface of the semiconductor device during the above processes. FIG. 3 is a schematic view illustrating a semiconductor device which illustrates a current leakage phenomenon between the ESD p-well 11 formed near the pad of the semiconductor substrate 1 and the main p-well 91 formed on the center portion of the semiconductor substrate 1 by the charging-up operation.
Namely, FIG. 3 illustrates the ESD p-well 11 connected with the pad 31 in the semiconductor substrate 1 and the main p-well 91 for forming a semiconductor device. The first insulation layer 15, the second insulation layer 16, the protection layer 17, and the planarizing layer 18 are sequentially deposited on the upper surface of the semiconductor substrate 1. A high voltage of about 9V is applied to the ESD p-well 11 through the pad 31 and the main p-well 91 is connected with the ground. Th negative electric charges are accumulated on the upper surface of the planarizing layer 18, and the electric charges are trapped in the interfaces between the first and second insulation layers 15 and 16, the protection layer 17, and the planarizing layer 18, so that positive electric charges are induced on the surface of the semiconductor substrate, and the depletion layer is formed on the surface of the n-type semiconductor substrate. As the positive electric charges are induced on the surface of the semiconductor substrate 1, a p-channel effect is formed between the ESD p-well 11 and the main p-well 91. Therefore, when a high voltage is applied to the ESD p-well 11, a current is leaked between the ESD p-well 11 and the main p-well 91, so that a direct current (DC) error occurs in the semiconductor device.
In addition, since the positive electric charges are induced on the surface of the semiconductor, the threshold voltage is varied, and the malfunction may occur in the semiconductor device.
Furthermore, while the electric charges are moving along the polysilicon or metallic wiring portion, the electric charges may damage a weak portion of the semiconductor device such as a gate oxide film, etc.
In addition, the charge-up may be concentrated on the center portion of the wafer rather than on the margin portions, so that the characteristic of the semiconductor device may be changed in accordance with the position of the semiconductor device.